Here is the DTMF (Dual Tone Multiple Frequency) application is associated with digital telephony, and provides two selected output frequencies (one high band, one low band) for a duration of 100 ms. A benchmark subroutine has been written for the COP820C/840C microcontrollers, and is outlined in detail in this application note.source

This circuit outlines two different methods of DTMF generation using a COP820C/840C microcontroller clocked with a 3.58 MHz crystal in the divide by 10 mode. This yields an instruction cycle time of 2.79 ms. The application note also provides a low true row/column decoder for the DTMF keyboard. The first method of DTMF generation provides two PWM (Pulse Width Modulation) outputs on pins G3 and G2 of the G port for 100 ms. These two PWM outputs represent the selected high band and low band frequencies respectively, and must be combined externally with an LM324 op amp or equivalent feed back circuit to produce the DTMF signal. The second method of DTMF generation uses ROM lookup tables to simulate the two selected DTMF frequencies.source

The DDS chip is programmed by sending a 32-bit control word, and bam, there is the signal, clean and on frequency. The kit documentation points you to a site here you can download a Visual Basic program to program the DDS via the parallel port of a PC.source

This signal generator uses a three channel DAC to generate Composite video signal (CVBS) and S video signal (Y/C separated) at the same time, left one channel is not used in NTSC format. It is assigned for one of the color components of Y/CB/CR video format. This feature was not planned some years ago, but it has been added when started to draw the schematic this year, because NTSC television system might be obsoleted in the near future. The two different video format, component video and NTSC video, work in exclusive.source

This schematic illustrates dividing a crystal oscillator signal by the crystal frequency to obtain an accurate (0.01%) 1 second time base. Two cascaded 12 stage counters (CD4040) form a 24 stage binary counter and the appropriate bits are gated together to produce the desired division. Using a crystal of some even multiple of 2 is desirable so that one stage of the counter automatically toggles every second which eliminates the need for the NAND gate and reset circuitry, however the circuit below illustrates using a crystal which is not an even multiple of 2 and so requires additional components.source